リンク集
目次
- Intel® 64 and IA-32 Architectures Software Developer Manuals
- Intel 日本語技術資料のダウンロード
- AMD Developer Guides, Manuals & ISA Documents
- x86 calling conventions - Wikipedia
- x64 でのソフトウェア規約
- System V Application Binary Interface - Intel386 Architecture Processor Supplement
- System V Application Binary Interface - AMD64 Architecture Processor Supplement
- How to optimize for the Pentium family of the microprocessors (In Japanese)
- Software optimization resources
- The Intel 80386, part 1: Introduction
- The Intel 80386, part 2: Memory addressing modes
- The Intel 80386, part 3: Flags and condition codes
- The Intel 80386, part 4: Arithmetic
- The Intel 80386, part 5: Logical operations
- The Intel 80386, part 6: Data transfer instructions
- The Intel 80386, part 7: Conditional instructions and control transfer
- The Intel 80386, part 8: Block operations
- The Intel 80386, part 9: Stack frame instructions
- The Intel 80386, part 10: Atomic operations and memory alignment
- The Intel 80386, part 11: The TEB
- The Intel 80386, part 12: The stuff you don’t need to know
- The Intel 80386, part 13: Calling conventions
- The Intel 80386, part 14: Rescuing a stack trace after the debugger gave up when it reached an FPO function
- The Intel 80386, part 15: Common compiler-generated code sequences
- The Intel 80386, part 16: Code walkthrough
- The Intel 80386, part 17: Future developments
- ARM Developer Suite Assembler Guide
- Writing ARM64 Code for Apple Platforms
- The ARM processor (Thumb-2), part 1: Introduction
- The ARM processor (Thumb-2), part 2: Differences between classic ARM and Thumb-2
- The ARM processor (Thumb-2), part 3: Addressing modes
- The ARM processor (Thumb-2), part 4: Single-instruction constants
- The ARM processor (Thumb-2), part 5: Arithmetic
- The ARM processor (Thumb-2), part 6: The lie hiding inside the CMN instruction
- The ARM processor (Thumb-2), part 7: Bitwise operations
- The ARM processor (Thumb-2), part 8: Bit shifting and bitfield access
- The ARM processor (Thumb-2), part 9: Sign and zero extension
- The ARM processor (Thumb-2), part 10: Memory access and alignment
- The ARM processor (Thumb-2), part 11: Atomic access and barriers
- The ARM processor (Thumb-2), part 12: Control transfer
- The ARM processor (Thumb-2), part 13: Trampolines
- The ARM processor (Thumb-2), part 14: Manipulating flags
- The ARM processor (Thumb-2), part 15: Miscellaneous instructions
- The ARM processor (Thumb-2), part 16: The calling convention
- The ARM processor (Thumb-2), part 17: Prologues and epilogues
- The ARM processor (Thumb-2), part 18: Other kinds of prologues and epilogues
- The ARM processor (Thumb-2), part 19: Common patterns
- The ARM processor (Thumb-2), part 20: Code walkthrough
- 32ビット PowerPC アーキテクチャ プログラミング環境 (PDF)
- PowerPC Compiler Writer's Guide
- PowerPCアセンブリー
- Assembly language for Power Architecture, Part 1: Programming concepts and beginning PowerPC instructions
- Assembly language for Power Architecture, Part 2: The art of loading and storing on PowerPC
- Power アーキテクチャーのためのアセンブリー言語: 第 3 回: PowerPC 分岐プロセッサーでのプログラミング
- Power アーキテクチャーのためのアセンブリー言語 第 4 回: 関数コールと PowerPC の 64-ビット ABI
- The PowerPC 600 series, part 1: Introduction
- The PowerPC 600 series, part 2: Condition registers and the integer exception register
- The PowerPC 600 series, part 3: Arithmetic
- The PowerPC 600 series, part 4: Bitwise operations and constants
- The PowerPC 600 series, part 5: Rotates and shifts
- The PowerPC 600 series, part 6: Memory access
- The PowerPC 600 series, part 7: Atomic memory access and cache coherency
- The PowerPC 600 series, part 8: Control transfer
- The PowerPC 600 series, part 9: The table of contents
- The PowerPC 600 series, part 10: Passing parameters, function prologues and epilogues
- The PowerPC 600 series, part 11: Glue routines
- The PowerPC 600 series, part 12: leaf functions
- The PowerPC 600 series, part 13: Common patterns
- The PowerPC 600 series, part 14: Code walkthrough
- MIPS Architectures
- The MIPS R4000, part 1: Introduction
- The MIPS R4000, part 2: 32-bit integer calculations
- The MIPS R4000, part 3: Multiplication, division, and the temperamental HI and LO registers
- The MIPS R4000, part 4: Constants
- The MIPS R4000, part 5: Memory access (aligned)
- The MIPS R4000, part 6: Memory access (unaligned)
- The MIPS R4000, part 7: Memory access (atomic)
- The MIPS R4000, part 8: Control transfer
- The MIPS R4000, part 9: Stupid branch delay slot tricks
- The MIPS R4000, part 10: Trampolines and stubs
- The MIPS R4000, part 11: More on branch delay slots
- The MIPS R4000, part 12: Calling convention
- The MIPS R4000, part 13: Function prologues and epilogues
- The MIPS R4000, part 14: Common patterns
- The MIPS R4000, part 15: Code walkthrough
- The Alpha AXP, part 1: Initial plunge
- The Alpha AXP, part 2: Integer calculations
- The Alpha AXP, part 3: Integer constants
- The Alpha AXP, part 4: Bit 15. Ugh. Bit 15.
- The Alpha AXP, part 5: Conditional operations and control flow
- The Alpha AXP, part 6: Memory access, basics
- The Alpha AXP, part 7: Memory access, loading unaligned data
- The Alpha AXP, part 8: Memory access, storing bytes and words and unaligned data
- The Alpha AXP, part 9: The memory model and atomic memory operations
- The Alpha AXP, part 10: Atomic updates to byte and word memory units
- The Alpha AXP, part 11: Processor faults
- The Alpha AXP: Part 12: How you detect carry on a processor with no carry?
- The Alpha AXP, part 13: On treating a 64-bit processor as if it were a 32-bit processor
- The Alpha AXP, part 14: On the strange behavior of writes to the zero register
- The Alpha AXP, part 15: Variadic functions
- The Alpha AXP, part 16: What are the dire consequences of having 32-bit values in non-canonical form?
- The Alpha AXP, part 17: Reconstructing a call stack
- The Alpha AXP, epilogue: A correction about file system compression on the Alpha AXP
- The Itanium processor, part 1: Warming up
- The Itanium processor, part 2: Instruction encoding, templates, and stops
- The Itanium processor, part 3: The Windows calling convention, how parameters are passed
- The Itanium processor, part 4: The Windows calling convention, leaf functions
- The Itanium processor, part 3b: How does spilling actually work?
- The Itanium processor, part 5: The GP register, calling functions, and function pointers
- The Itanium processor, part 6: Calculating conditionals
- The Itanium processor, part 7: Speculative loads
- The Itanium processor, part 8: Advanced loads
- The Itanium processor, part 9: Counted loops and loop pipelining
- The Itanium processor, part 10: Register rotation
- The SuperH-3, part 1: Introduction
- The SuperH-3, part 2: Addressing modes
- The SuperH-3, part 3: Status flags and miscellaneous instructions
- The SuperH-3, part 4: Basic arithmetic
- The SuperH-3, part 5: Multiplication
- The SuperH-3, part 6: Division
- The SuperH-3, part 7: Bitwise logical operations
- The SuperH-3, part 8: Bit shifting
- The SuperH-3, part 9: Constants
- The SuperH-3, part 10: Control transfer
- The SuperH-3, part 11: Atomic operations
- The SuperH-3, part 12: Calling convention and function prologues/epilogues
- The SuperH-3, part 13: Misaligned data, and converting between signed vs unsigned values
- The SuperH-3, part 14: Patterns for function calls
- The SuperH-3, part 15: Code walkthough
- The AArch64 processor (aka arm64), part 1: Introduction
- The AArch64 processor (aka arm64), part 2: Extended register operations
- The AArch64 processor (aka arm64), part 3: Addressing modes
- The AArch64 processor (aka arm64), part 4: Addition and subtraction
- The AArch64 processor (aka arm64), part 5: Multiplication and division
- The AArch64 processor (aka arm64), part 6: Bitwise operations
- The AArch64 processor (aka arm64), part 7: Bitfield manipulation
- The AArch64 processor (aka arm64), part 8: Bit shifting and rotation
- The AArch64 processor (aka arm64), part 9: Sign and zero extension
- The AArch64 processor (aka arm64), part 10: Loading constants
- The AArch64 processor (aka arm64), part 11: Loading addresses
- The AArch64 processor (aka arm64), part 12: Memory access and alignment
- The AArch64 processor (aka arm64), part 13: Atomic access
- The AArch64 processor (aka arm64), part 14: Barriers
- The AArch64 processor (aka arm64), part 15: Control transfer